1. Field of the Invention
The present invention relates to signal amplifiers and, particularly, to a signal amplifier having a noninverting amplifier and an inverting amplifier connected in series.
2. Description of Related Art
A voltage amplifier where a source follower and an inverter, which is typically an n-channel metal-oxide semiconductor (NMOS), are connected in series is used to amplify a micro charge detection signal in a charge-coupled device (CCD) or the like. The voltage amplifier, however, has a larger signal delay than a buffer or the like where a plurality of source followers are connected in series, which is used when not amplifying the voltage, and it is therefore not compatible with high-speed signals with a high frequency band. As a decrease in a CCD imaging time is required recently, a demand for a voltage amplifier with high speed and high voltage signal gain is increasing.
The configuration of a conventional voltage amplifier is described hereafter with reference to FIG. 6. This voltage amplifier has a clamp capacitor C1, inverters 2 and 3, and a clamp circuit 6, which are connected between a signal input terminal 11 and a signal output terminal 12. A power supply voltage VDD is supplied to each device.
One end of the clamp capacitor C1 is connected to the signal input terminal 11 and the other end is connected to a node N5. The node N5 is an input terminal of the inverter 2. The clamp capacitor C1 blocks the DC path between the signal input terminal 11 and the node N5 and transmits to the node N5 the AC component of an input signal Vin from the signal input terminal 11.
The inverter 2 has NMOS transistors M3 and M4. The transistor M3 has the drain and the gate connected to the power supply VDD and the source connected to the node N2. The transistor M4 has the drain connected to the node N2, the gate connected to the node N5, and the source connected to the ground GND. In the inverter 2, the transistor M4 is a drive transistor and the transistor M3 is a load transistor. The inverter 2 inverts and amplifies the voltage signal from the node N5 and outputs it to the node N2, which is the input terminal of the inverter 3 in the subsequent stage.
The inverter 3 has transistors M5 and M6. The transistor M5 has the drain and the gate connected to the power supply VDD and the source connected to the signal output terminal 12. The transistor M6 has the drain connected to the signal output terminal 12, the gate connected to the node N2, and the source connected to the ground voltage GND. In the inverter 3, the transistor M6 is a drive transistor and the transistor MS is a load transistor. The inverter 3 inverts and amplifies the voltage signal output from the inverter 2 and outputs an output signal Vout to the signal output terminal 12.
The drive transistor M6 of the inverter 3 has a higher threshold voltage than the drive transistor M4 of the inverter 2. The transistors M3 and M5 have the same threshold voltage as the transistor M4.
The clamp circuit 6 has transistors M12 to M15. The transistors M12 and M14 each have the drain and the gate connected to the power supply VDD, and the source connected to the node N6. The transistor M13, which constitutes a voltage divider, has the drain and the gate connected to the node N6 and the source connected to the ground GND. The output terminal or the voltage dividing terminal of the voltage divider is the node N6. The transistor M15 has one of the source and the drain connected to the node N5, the other one of the source and the drain connected to the node N6, and the gate connected to the clamp control terminal 13.
The clamp circuit 6 determines the input offset voltage of the inverter 2, which is the voltage at the node N5. The transistor M15 is a clamp switching transistor and it is turned on or off by a control signal φCLP from the clamp control terminal 13. The transistor M14 has the same threshold voltage as the transistor M6 of the inverter 3. The transistors M12 and M13 have the same threshold voltage as the transistor M4 of the inverter 2. The transistor M15 may have any threshold voltage as long as it is capable of switching operation.
The clamp operation of the clamp circuit 6 is described below. The input signal Vin from the signal input terminal 11 is AC-coupled by the clamp capacitor C1 and input to the inverter 2. Further, the ON signal is input from the clamp control terminal 13 to turn on the clamp switching transistor M15, and the voltage V5 of the node N5, which is the input terminal of the inverter 2, thereby becomes equal to the voltage V6 of the node N6, which is the output terminal of the voltage divider. However, since the voltage V5 is fixed to a constant level in this state, the AC component of the voltage signal input to the signal input terminal 11 is not input to the inverter 2. Thus, upon input of the signal, the control signal φCLP is OFF to turn off the clamp switching transistor M15, and the voltage V5 varies according to the voltage of the input signal Vin with the offset voltage kept the same as the voltage V6.
The amplifying operation of the inverters 2 and 3 is described hereafter with reference to FIG. 7. FIG. 7 shows the input and output characteristics of the inverters 2 and 3. In the graph of FIG. 7, the horizontal axis indicates an input voltage and the vertical axis indicates an output voltage. The dotted line 701 and the solid line 702 show the characteristics of the inverter 2 and the inverter 3, respectively. The input voltage of the inverter 2 is the voltage V5 at the node N5, and the output voltage of the inverter 2 is the voltage V2 at the node N2. The input voltage of the inverter 3 is the voltage V2 at the node N2, and the output voltage of the inverter 3 is the voltage Vout at the signal output terminal 12. The region which has a constant gain for the input voltage and outputs an output voltage is called an amplification region.
If the threshold voltages of the transistors M4 and M6 are Vt1 and Vt2, respectively, the transistors M4 and M6 are not turned on and thus the inverters 2 and 3 do not perform inversion and amplification until the input voltages V5 and V2 of the inverters 2 and 3 reach the voltage levels Vt1 and Vt2, respectively. When the input voltages V5 and V2 exceed the voltage levels Vt1 and Vt2, the inverters 2 and 3 perform inversion and amplification. Thus, the region where the voltage exceeding the threshold voltage of each drive transistor is input is the amplification region of the inverter.
However, if the input voltages exceed the voltage levels Vd1 and Vd2 of FIG. 7, the inversion and amplification are stopped since the transistors M4 and M6 enter the triode region, and therefore the output voltages V2 and Vout become constant. As in FIG. 7, when the threshold voltages of the drive transistor are high and low, if the input offset voltage is the same, the output offset voltage is higher where the threshold voltage is higher; on the other hand, if the input offset voltage is higher for the higher threshold voltage, the output offset voltage is the same where the threshold voltages are high and low.
Referring next to FIG. 8, the operation when the inverters 2 and 3 are connected in series is described. FIG. 8 shows the input and output characteristics of the inverters 2 and 3 which are connected in series as in the configuration of FIG. 6. In the graph of FIG. 8, the first quadrant and the second quadrant show the input and output characteristics of the inverter 2 and the inverter 3, respectively. In the second quadrant, the dotted line 801 and the solid line 802 show the input and the output characteristics when the threshold voltage of the driver transistor M6 is Vt1 and Vt2, respectively.
A clamp voltage VC1 is applied so as to be the center of the amplification region. The input voltage V5 superposed with a clamp offset voltage VC5 is amplified and the output voltage V2 is transmitted to the inverter 3. If the threshold voltage of the drive transistor M6 of the inverter 3 is Vt1 shown by the dotted line 801, which is the same as the threshold voltage of the transistor M4 of the inverter 2, part or entire input signal may exceed Vd1. In this case, the part of the signal exceeding the amplification region is not amplified, such as the signal with the offset level VCout2 shown by the dotted line 803 in the second quadrant, and the input signal is not properly amplified. If, on the other hand, the threshold voltage of the drive transistor M6 of the inverter 3 is set to Vt2 as shown by the solid line 802, it is possible to set the entire input signal to be within the amplification region. In this case, the input signal is properly amplified, such as the signal with the offset level VCout shown by the solid line 804 in the second quadrant, to generate the output signal Vout.
When forming the circuit of FIG. 6 in an actual semiconductor device, the threshold voltage of the transistor may vary by manufacturing parameter variation such as uneven amount of ion implantation. In the circuit configuration of FIG. 6, only the transistor M14 of the clamp circuit 6 and the transistor M6 of the inverter 3 are the transistors having the same threshold voltage. Thus, even if the threshold voltage variation such as shown by the solid line 702 and the dotted line 701 of FIG. 7 occurs in the inverter 3, for example, and the input offset voltage varies according to the characteristics variation, the voltage is always about the center of the amplification region of the inverter 3.
Conventional voltage amplifiers are described in Japanese Unexamined Patent Application Publication No. 2001-211393, 2003-017959, and 60-254904, for example.
However, the present invention has recognized that the above conventional voltage amplifies require the clamp circuit 6 and the clamp control signal φCLP for adjusting the input offset voltage, which causes the drive circuit of the device to be more complicated.
Further, since the conventional voltage amplifiers use the clamp circuit 6, it requires the clamp capacitor C1 for AC-coupling or DC-cutting the signal input terminal 11 and the node N5 of the input terminal of the inverter 2. Parasitic impedance such as the capacitance of the capacitor C1 and the line resistance thereby increases, which results in higher input capacitance of the voltage amplifier of FIG. 6. In the voltage amplifier having the circuit of FIG. 6, this reduces the speed (used frequency band) of the entire voltage amplifier due to a time constant increase in a charge and discharge time of the circuit in the previous stage of the clamp, such as a source follower.
Furthermore, the DC-cutting in the clamp capacitor causes the amplitude or gain of the input signal Vin to decrease in the node N5. This is because the voltage signal is divided by the parasitic capacitance of the capacitor C1 and the node N5, such as line capacitance of the node N2, gate capacitance of the transistor M4, gate-drain capacitance, gate-source capacitance, diffusion layer capacitance in the drain or the source of the transistor M15, and diffusion layer-gate capacitance. This impedes achievement of higher gain and higher speed operation particularly in voltage amplifiers.